1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device for improving a reliability of memory cells in a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
2. Description of the Background Art
As shown in FIG. 23, a DRAM has one-transistor and one-capacitor structure including one MOS transistor 27 and one capacitor 28. A voltage equal to or higher than a predetermined threshold voltage is applied to a gate electrode of the MOS transistor so that electric charges are accumulated in or discharged from the capacitor. Through these operations, data is held, written or read.
A conventional method of manufacturing a DRAM will be described below with reference to Japanese Patent Laying-Open No. 2-143456 (1990).
Referring to FIG. 24, an element isolating and insulating film 2 is formed on a silicon substrate 1 by a trench isolating method. Element isolating and insulating film 2 defines a plurality of regions for forming MOS transistors and others on silicon substrate 1. A gate oxide film 3 is formed by a thermal oxidation method. A polycrystalline silicon film 4 and a silicon oxide film 5 are formed. Gate electrode portions 6 are formed by anisotropic etching effected on polycrystalline silicon film 4 and silicon oxide film 5 masked with a predetermined photoresist. Ion implantation is performed to from nxe2x88x92source/drain regions 7a, 7b, 7c and 7d. 
Referring to FIG. 25, a side wall 8 is formed on a side surface of each gate electrode portion 6. An ion implantation method is performed to form n+-source/drain regions 9a, 9b, 9c and 9d. Thereby, source electrode portions 10a and 10b as well as drain electrode portions 11a and 11b are formed.
Referring to FIG. 26, a chemical vapor deposition method or the like is performed to form epitaxial silicon layers 12a and 12b only on source electrode portions 10a and 10b. Epitaxial silicon layers 12c and 12d are formed on only drain electrode portions 11a and 11b. Epitaxial silicon layers 12a, 12b, 12c and 12d thus formed have top surfaces located higher than tops surfaces of silicon oxide films 5 of the gate electrode portions, and protrude over side walls 8 and element isolating and insulating film 2.
Referring to FIG. 27, an insulating film 13a is formed by a chemical vapor deposition method or the like.
Referring to FIG. 28, bit line contacts 14 and bit lines 15 are formed. An insulating film 13b covering bit lines 15 is formed on insulating film 13a. Storage node contacts 16a and 16b as well as storage nodes 17a and 17b are formed. A cell plate 19 is formed on storage nodes 17a and 17b with a high capacity insulating film layer 18 therebetween. Storage node 17a, high capacity insulating film layer 18 and cell plate 19 form one capacitor 20. Thereafter, metal interconnections and others are formed on capacitor 20 with an interlayer insulating film layer therebetween. In the foregoing manner, the semiconductor device is completed.
The above method of manufacturing the semiconductor device suffers from the following problem. First, as shown in FIG. 29, epitaxial silicon layers 12a and 12b are gradually formed only on n+-source/drain regions 9b and 9c after the step in FIG. 25, respectively.
As shown in FIG. 30, epitaxial silicon layers 12a and 12b continuously grow over surfaces of element isolating and insulating film 2 and side wall 8. Finally, as shown in FIG. 31, epitaxial silicon layers 12a and 12b cover the entire surface of side wall 8 and a part of the upper surface of element isolating and insulating film 2.
It has been reported in Journal of Crystal Growth 111 (1991), pp. 860-863 that polycrystalline silicon pieces 21 are generated on element isolating and insulating film 2, silicon oxide film 5 and others when the thicknesses of epitaxial silicon layers 12a and 12b exceed a predetermined value.
According to this reference, a material gas of, e.g., Si2H6 collides with the surface of the silicon oxide film during growth of the epitaxial silicon layer, and a part of the material gas decomposes into adatoms on the surface of the silicon oxide film. When the surface of the silicon oxide film is covered by these adatoms to a certain extent, polycrystalline silicon grows around adatoms serving as nuclei. Thus, the grown polycrystalline silicon changes into polycrystalline silicon pieces.
In typical formation of the epitaxial silicon layer, it can be estimated that this threshold thickness is about 150 nm. Lateral protrusion Gs of about 60 nm occurs at this time as shown in FIG. 31.
In the case of the 1-gigabit DRAM, it is estimated that gate electrode portion 6 has a height Hg of about 200 nm and an element isolating and insulating film 2 has a width Wt of about 200 nm. In this case, a thickness equal to or larger than threshold thickness Ts is required for forming epitaxial silicon layers 12a and 12b. 
If film thickness Ts is 200 nm, lateral protrusion Gs is about 80 nm. If the element isolating width is 200 nm, a space Ds of only about 40 nm is left between epitaxial silicon layers 12a and 12b. Polycrystalline silicon pieces 21 are generated on element isolating and insulating film 2 between epitaxial silicon layers 12a and 12b. 
If polycrystalline silicon pieces 21 thus generated are in contact with each other and are also in contact with epitaxial silicon layers 12a and 12b (i.e., in the case A), neighboring epitaxial silicon layers 12a and 12b are short-circuited together in this step.
In the other cases including a case B that some of polycrystalline silicon pieces 21 generated in the above step are spaced from the other polycrystalline silicon pieces, neighboring epitaxial silicon layers 12a and 12b are electrically insulated from each other for the time being.
In a next step, insulating film 13a is formed over neighboring epitaxial silicon layers 12a and 12b. Generally, in processing of forming an insulating film covering a portion between two neighboring patterns, the insulating film may not cover the above portion and a so-called void may be formed if a space between the neighboring convex patterns is relatively small. Particularly, in the case of a 1-gigabit DRAM, the epitaxial silicon layer has film thickness Ts of about 200 nm, and space Ds of about 40 nm is left between neighboring epitaxial silicon layers 12a and 12b as already described. Therefore, an aspect ratio between neighboring epitaxial silicon layers 12a and 12b is about 5, so that a void is very liable to be generated.
As shown in FIG. 32, if a void is formed between neighboring epitaxial silicon layers 12a and 12b, epitaxial silicon layers 12a and 12b, which were electrically insulated from each other, e.g., in the foregoing case B, may be short-circuited due to polycrystalline silicon pieces 21 which are present in the void and are brought into contact with each other due to some reasons after mounted in a product.
If a void is not formed, and particularly in the case B or the like, each polycrystalline silicon piece is buried in the insulating film, so that neighboring epitaxial silicon layers 12a and 12b are electrically insulated from each other. In the case A, however, the neighboring epitaxial silicon layers remain in the short-circuited state even if each polycrystalline silicon piece is buried in the insulating film.
As already described, a plurality of polycrystalline silicon pieces are generated during formation of the epitaxial silicon layers, so that the neighboring epitaxial silicon layers may be short-circuited together through the plurality of polycrystalline silicon pieces. Due to presence of the void, the neighboring epitaxial silicon layers may be further short-circuited through the polycrystalline silicon pieces in the void.
Accordingly, the DRAM suffers from a low reliability.
The invention has been developed for overcoming the above problems, and an object of the invention is to prevent short-circuit between transistors in neighboring memory cells and thereby provide an electrically reliable semiconductor device and another object of the invention is to provide a method of manufacturing the same.
According to an aspect of the present invention, a semiconductor device includes an element isolating and insulating film, a first doped region and a second doped region, a first epitaxial growth layer and a second epitaxial growth layer, and an insulating layer. The element isolating and insulating film is formed at a main surface of a semiconductor substrate. The first doped region and the second doped region are each formed at a main surface of a region of the semiconductor substrate with the element isolating and insulating film interposed therebetween. The first epitaxial growth layer and the second epitaxial growth layer are formed by selective, epitaxial growth of silicon or silicon-germanium alloy on the first doped region and the second doped region. The insulating layer is formed to cover at least a surface of the first and second epitaxial growth layers.
According to this structure, an insulting layer is formed to cover at least a surface of the first and second epitaxial growth layers. Thus, a short-circuit is not readily caused between the first and second epitaxial growth layers. Consequently, the electrical isolation between the first and second doped regions is improved.
Preferably, the insulating layer is formed by thermally oxidizing the first and second epitaxial growth layers.
In this case, a uniform, isolating layer is formed on a surface of the first and second epitaxial growth layers. Thus, the electrical isolation between the first and second doped regions is further improved.
Still preferably, the semiconductor device has a transistor having a pair of source/drain regions and a gate electrode each formed on a main surface of a region of the semiconductor substrate with the element isolating and insulating film disposed therebetween, and the first doped region includes one source/drain region of one transistor and the second doped region includes one source/drain region of the other transistor.
In this case, the electrical insulating performance of transistors formed at their respective regions of the semiconductor substrate with the element isolating and insulating film interposed therebetween, is improved.
According to another aspect of the invention, a method of manufacturing a semiconductor device includes the following steps. A plurality of element formation regions electrically isolated from each other by an element isolating and insulating film is formed at a main surface of a semiconductor substrate. A pair of source/drain regions spaced by a predetermined distance is formed at the element formation regions opposed to each other with the element isolating and insulating film therebetween, respectively. A gate electrode is formed on a region located between the paired source and drain regions at the main surface with a gate insulating film therebetween. An epitaxial growth step is performed to form epitaxial layers by selective epitaxial growth of silicon or silicon-germanium alloy on the surfaces of the source/drain regions. Inter-element insulating processing is effected on the main surface of the semiconductor substrate to oxidize or remove polycrystalline silicon generated in the epitaxial growth step for electrically insulating the epitaxial layers opposed to each other with the element isolating and insulating film therebetween. After the inter-element insulating step, an interlayer insulating film is formed at the main surface of the semiconductor substrate.
According to this method, an MOS transistor including a pair of source/drain regions and a gate electrode is formed at each of the regions at the main surface of the semiconductor substrate opposed to each other with the element isolating and insulating film therebetween. In the epitaxial growth step, silicon pieces adhere onto the element isolating and insulating film between the epitaxial silicon layers which are formed at the source/drain regions of the neighboring MOS transistors, respectively. However, the silicon pieces are oxidized or removed in the inter-element insulating step, so that short-circuit between the source/drain regions of the neighboring MOS transistors is prevented. As a result, the semiconductor device can have a good electrical reliability.
Preferably, the method further includes the following steps between the inter-element insulating step and the step of forming the interlayer insulating film. Processing is performed to form a bit line electrically connected to one of the paired source and drain regions. Also, processing is performed to form a capacitor electrically connected to the other of the paired source and drain regions.
The memory cell thus formed has a structure of one-transistor and one-capacitor.
More preferably, the inter-element insulating step includes a first oxidizing step of exposing the surface of the semiconductor substrate including a surface of the selectively grown silicon to an atmosphere containing oxygen.
In this case, the semiconductor substrate is exposed to the atmosphere including oxygen, so that surfaces of silicon pieces react with oxygen to form silicon oxide films. Thereby, each of polycrystalline silicon pieces is electrically insulated. Simultaneously, a silicon oxide film is formed at the surface of the epitaxially grown silicon. This improves an electrical insulating performance between the source/drain regions of the neighboring MOS transistors. Consequently, it is possible to provide a semiconductor device having a further improved electrical reliability.
More preferably, the inter-element insulating step further includes, after the first oxidizing step, a hydrofluoric acid treatment step of immersing the semiconductor substrate in a solution containing hydrofluoric acid or exposing the semiconductor substrate to a gas containing hydrofluoric acid.
In this case, the treatment with the hydrofluoric acid removes a silicon oxide film formed at the surface of the epitaxial layer and silicon oxide films formed around silicon pieces. In some cases, the silicon oxide film may not be sufficiently formed at the surface of the epitaxial layer, and the polycrystalline silicon pieces poor in an electrical insulating performance may be present at the surface. Even in these cases, all polycrystalline silicon pieces including the above polycrystalline silicon pieces are removed, so that the electrical insulating performance between the source/drain regions of the neighboring MOS transistors is further improved. As a result, the semiconductor device can have a further improved electrical reliability.
More preferably, the inter-element insulating step further includes, after the hydrofluoric acid treatment step, a second oxidizing step of exposing the surface of the semiconductor substrate to an atmosphere containing oxygen.
In this case, a silicon oxide film is formed at the surface of the epitaxial layer. This securely provides an electrical insulation between the source/drain regions of the neighboring MOS transistors. As a result, the semiconductor device can have an improved electrical reliability.
More preferably, the inter-element insulating step includes the following steps. A metal film is formed at the surface of the semiconductor substrate including a surface of the selectively grown silicon. A heat treatment is effected on the semiconductor substrate including the metal film. The metal film is removed after the heat treatment.
In this case, the metal film is formed on the semiconductor substrate including the neighboring MOS transistors. Owing to the heat treatment at a predetermined temperature, silicon in the epitaxial layer and the metal layer react with each other to form a metal silicide film. Since silicon pieces are extremely small in quantity, they diffuse into the metal film. Thereafter, the metal film is removed. Thereby, the source/drain regions of the neighboring MOS transistors are electrically insulated from each other. As a result, the semiconductor device can have an improved electrical reliability.
The metal film may be made of titanium, cobalt, zirconium or hafnium. The step of removing the metal film includes a step of immersing the semiconductor substrate in a mixture solution of sulfuric acid and hydrogen peroxide.
More preferably, the inter-element insulating step further includes a third oxidizing step of exposing the semiconductor substrate to an atmosphere containing oxygen after removing the metal film.
In this case, a silicon oxide film is formed at the surface of the epitaxial layer. This surely provides an electrical insulation between the source/drain regions of the neighboring MOS transistors. As a result, the semiconductor device can have an improved electrical reliability.
More preferably, the inter-element insulating step includes the following steps. An insulating film is formed at a predetermined region of the element isolating and insulating film. The insulating film is removed after the epitaxial growth step.
In this case, the insulating film is formed at the surface of the predetermined region of the element isolating and insulating film. In the process of epitaxial growth, epitaxial layers are formed at surfaces of the source/drain regions of the neighboring MOS transistors, respectively. Silicon pieces adhere onto the insulating film between these epitaxial layers. When removing the insulating film, the silicon pieces are simultaneously removed. This further improves the insulating performance between the source/drain regions of the neighboring MOS transistors. As a result, the semiconductor device can have an improved electrical reliability.
The above insulating film may be a silicon nitride film. The step of removing the insulating film includes a step of removing the silicon nitride film with a solution containing phosphoric acid.
More preferably, the inter-element insulating step further includes a fourth oxidizing step of exposing the semiconductor substrate to an atmosphere containing oxygen after removing the insulating film.
In this case, a silicon oxide film is formed at the surface of the epitaxial layer. This surely provides an electrical insulation between the source/drain regions of the neighboring MOS transistors. As a result, the semiconductor device can have an improved electrical reliability.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.